The present invention relates generally to improving reliability of differentially coupled input transistors of a comparator or amplifier, and more particularly to preventing damage caused by hot carrier injection (HCI), and especially to preventing HCI due to excessive reverse bias of base-emitter junctions of differentially coupled input transistors of the comparator or amplifier or excessive gate-source voltages of differentially coupled field effect input transistors of the comparator or amplifier.
A comparator is a circuit that determines whether its input signal is higher (or lower) than a fixed or varying reference signal and accordingly switches its output to a high (or low) logic level. A comparator need not be as multi-functional as an operational amplifier, but a comparator needs to respond faster than an operational amplifier, and do so with a smaller magnitude input overdrive voltage (i.e., with a smaller difference between the input voltage to one input of the comparator and a reference voltage applied to the other input of the comparator). For a comparator, this is an advantage because phase margin and unity gain stability are not of primary concern. A basic specification for a comparator is its comparator delay TDELAY, which is the time required for the comparator output to switch after detecting its minimum input overdrive voltage. Another specification is input overdrive voltage VOVDR, which is the minimum differential input voltage at which the comparator responds by switching its output signal. The minimum small signal gain of a comparator can be roughly calculated as VSUPPLY/VOVDR (input overdrive voltage). In order to achieve this gain at the necessary speed, at least two gain stages typically are required.
One of the important considerations of comparator design is the reliability of its input transistors. If a large signal differential voltage, e.g., greater than 2 volts, is applied at the inputs of a typical differential input transistor pair, the input transistor that is in its OFF or “cut-off” condition experiences a large emitter-base junction reverse bias voltage VEBO that exceeds 0.7 volt. This causes hot carrier generation (e.g., a tunneling or avalanche effect) in the base-emitter junction of that input transistor and may permanently degrade the current gain β and performance of the input transistor.
Prior Art FIG. 1 shows a typical differential input stage which includes differentially coupled PNP input transistors Q0 and Q1 having their emitters coupled to receive a tail current ITAIL, and also includes associated load devices 12 and 13. This differential input stage can be used in an operational amplifier. However, a problem with using this configuration as the input stage of a comparator is that when one of the input voltages Vin+ or Vin− is much more positive than the other (i.e., when a differential input voltage of large magnitude is applied to the comparator), all of the tail current ITAIL flows through one or the other of input transistors Q0 and Q1. If Vin− is much more negative than Vin+ all of the tail current ITAIL will flow through transistor Q1 and the voltage on the emitter of transistor Q1 is one VBE voltage (base-emitter voltage) greater than Vin−. For example, if Vin− is equal to +2 volts and VBE is equal to 0.7 volts, then the emitter of Q1 is approximately 2.7 volts. If Vin+ is equal to +5 volts, then the reverse bias of the emitter-base junction of the OFF transistor Q0 is equal to about 2.3 volts, which is a sufficiently large reverse bias to cause hot electron injection across the emitter-base junction of transistor Q0. In this example, the hot electron injection may the degrade performance of input transistor Q0.
This is especially true for modern wafer fabrication processes in which such hot electron injection is very likely to degrade the current gain β and hence the performance of the input transistors over time. (It is believed that injected high-energy or “hot” electrons become trapped in the emitter-base junction and thereby cause the above mentioned degradation of the β of the transistor.) This can cause the matching of input transistors Q0 and Q1 to change over time due to the effects of the above mentioned large reverse bias. That would result in permanent changing over time of the input offset voltage Vos of the differential input stage. That would be highly undesirable because it would cause the switching point of a comparator to change over time.
Similarly, if MOS input transistors are used instead of PNP input transistors Q0 and Q1, a similar large gate-source reverse bias voltage on the “cut-off” MOS input transistor can result in hot electron injection that may cause a shift in the turn-on threshold voltage VT of that input transistor. Differentially coupled JFET input transistors also may undergo undesirable permanent changes due to hot electron injection.
To overcome the hot electron injection problem described above, some comparators of the prior art use a CMOS input stage which can tolerate large reverse bias between the gate and source electrodes of an input transistor. Some previous comparators include differentially coupled bipolar input transistors that can tolerate large reverse bias across their emitter-base junctions. However, as device sizes have become smaller, transistors fabricated using some recent bipolar integrated circuit manufacturing processes do not have the ability to tolerate such large reverse bias across their base-emitter junctions, and a solution to the above mentioned hot electron injection problem is needed more than ever. Up to now, the hot electron injection problem in comparator input stages has been avoided mainly by using older wafer fabrication processes to fabricate bipolar transistors that are capable of withstanding the large emitter-base reverse bias voltages.
The closest prior art is also believed to include commonly owned U.S. Pat. No. 7,339,402 entitled “Differential Amplifier with Overvoltage Protection and Method” issued Mar. 4, 2008 to Alenin et al. Prior Art FIG. 1B herein is a copy of FIG. 5 of the '402 patent, and includes circuitry 11 for preventing damage to differentially coupled PNP transistors Q3 and Q4 in integrated circuit amplifier circuitry 10C during slew-limited operation. The emitters of transistors Q3 and Q4 are coupled by JFETs (junction field effect transistors) to receive amplifier input signals Vin+ and Vin+, respectively. A minimum voltage selector circuit 11 includes a “separator” JFET J3 which has a source terminal connected to the base of transistor Q3, and also coupled by a diode-connected transistor Q3B to the emitter of transistor Q3. The drain terminal of separator JFET J3 is connected to the base of transistor Q4 and also is coupled by a diode-connected transistor Q4B to the emitter of transistor Q4. The gate of separator JFET J3 is controlled by other circuitry in minimum voltage selector circuit 11 so as to electrically isolate the emitters of transistors Q3 and Q4, to thereby limit the amount of reverse bias across the emitter-base junction of one of those transistors. In the circuit shown in Prior Art FIG. 1B, the input JFETs J1 and J2 are depletion mode devices. But if JFETs J1 and J2 are replaced with NPN transistors, the common mode input range of operation for the circuit of Prior Art FIG. 1B requires more than two forward-biased base-emitter voltages in order to operate.
Thus, there is an unmet need for a differential input stage of a comparator or amplifier to prevent circuit degradation due to hot carrier injection resulting from large differential input voltages.
There also is an unmet need for a differential input stage of a comparator or amplifier to prevent circuit degradation due to hot carrier injection across the emitter-base junction of a bipolar (PNP or NPN) input transistor of the differential input stage resulting from large differential input voltages applied to the differential input stage.
There also is an unmet need for a differential input stage for a comparator or amplifier which prevents circuit degradation due to hot carrier injection in a field effect input transistor of the differential input stage resulting from large differential input voltages applied to the differential input stage.
There also is an unmet need for a differential input stage for a comparator or amplifier which is able to prevent reverse bias voltages that are sufficiently large to damage the input transistors, without causing large input currents, without large internal quiescent currents, and which allows the common mode voltage or the supply voltage of the comparator or amplifier to operate beyond maximum voltage levels that can be tolerated by unprotected input transistors.